This invention relates generally to booster circuits for use in semiconductor memory devices such as Flash EEPROM devices and more particularly, it relates to a boost level clamping circuit and method for clamping a boosted wordline voltage from a booster circuit used in a semiconductor memory device which is power supply and process corner independent.
In Flash EEPROM memory devices, it is often required voltages to be internally generated that are greater than an external or off-chip power supply potential VCC which is applied to it. For example, it is known that in the Flash EEPROM memory devices operating at the power supply potential VCC equal to +3.0 volts, a high voltage of approximately +5.0 volts is needed to be produced for the reading mode of operation of the memory cells. As a consequence, the semiconductor memories also generally include an internal voltage boosting circuit for generating an output signal boosted to be higher than the external power supply potential, which is supplied to a wordline driver circuit connected to the wordline.
One of the ways of saving power consumption is to operate the booster circuit only during the active period when the wordline is activated and not during the standby mode. As a result, for the boosting operation during the active period, the boosted voltage level must be raised very quickly from its original power supply level VCC in a short amount of time. Typically, the boosting circuit has only a small current drive capability and cannot perform adequately this operation, which reduces the operating speed of the semiconductor memory. In order to solve this problem, there has been attempted in the prior art of producing a larger boosting circuit for boosting the external power supply potential to be higher than the actual boosted voltage level required at the wordline so as to increase its speed of operation.
However, this larger boosting circuit is not without any shortcomings. Since the wordline voltage will now be possibly higher than what is required, there will be created increased stress (over-stressing) on the gates of the memory core transistors connected to the wordline. In order to solve this shortcoming, there has been developed in the prior art booster clamping circuits for clamping the boosted voltage level from the booster so as to prevent over-stressing of the wordline core transistor. Unfortunately this booster clamping circuit has slowed down the boosting speed of operation. Further, since the boosted voltage level applied to the wordline is created from the booster circuit, it will vary greatly with the power supply voltage VCC and process corners.
Accordingly, it would be desirable to provide a boost level clamping circuit for clamping a boosted wordline voltage from a booster circuit used in a semiconductor memory device which is independent of variations in the power supply potential and process corners. It would be expedient that the booster clamping circuit have a high reliability and a higher speed of operation. This is accomplished in the present invention by the provision of a booster level clamping circuit which is formed of a plurality of parallel-connected clamp stage circuits connected to the boosted wordline voltage from the booster circuit. Each of the plurality of clamp stages is used to clamp the boosted wordline voltage only when it reaches one of a number of different predetermined levels.